1. Field of Invention
The present invention relates to a method for fabricating a semiconductor. More particularly, the present invention relates to a fabrication method for a metal oxide semiconductor (MOS) transistor combining a dual threshold voltage process and a local channel implantation.
2. Description of Related Art
Conventionally, in the manufacture of the MOS transistor, a field oxide layer for defining an active region is formed in the substrate. An ion implantation step is then performed so that a well is formed in the active region, and two implantation regions are globally formed for providing a threshold voltage (V.sub.T) adjustment and an anti-punch through layer respectively. On the substrate, gates are formed with spacers located on sidewalls of the gate. Furthermore, source/drain (S/D) regions having lightly doped drains (LDD) are formed underneath both sides of the gate in the substrate. An implantation region, which provides the anti-punch through layer, is located below the S/D region, wherein a junction capacitance, which affects the efficiency of the device, exists between the implantation region and the S/D region.
As the integration of the device increases with a decrease in the line width, a shallow trench isolation (STI) becomes the necessary isolation structure for the device when the process advances to the technology of below 0.25 micron. However, different outcomes are produced due to the device characteristics if the field oxide layer is substituted with the STI to isolate the device.
It was known that if the field oxide layer serves as a device isolation structure, V.sub.T of the transistor increases when the length of the gate (i.e. channel length) increases. This is known as a short channel effect (SCE). As the width of the gate increases, V.sub.T of the transistor reduces as a consequence of a narrow channel effect (NCE). However, if the STI is substituted for device isolation, V.sub.T of the transistor increases at first and then decreases when the gate width gradually increases. This phenomenon is different from the outcome produced when the field oxide layer is used, and is therefore known as a reverse short channel effect (R-SCE). When the width of the gate increases, V.sub.T of the transistor increases as a consequence of a reverse narrow channel effect (R-NCE).
As the R-SCE and the R-NCE both occur in case where the STI is used, it becomes more difficult in terms of designing the gate when a transistor having different V.sub.T is designed during the dual threshold voltage process. Thus, it is not easy to control the efficiency of the device.
When the line width is reduced down to below 0.5 micron, the problem of the R-NCE gets worse. In particular, the process below 0.35 micron produces serious effect to the device. It was known that the V.sub.T adjustment and the anti-punch through layer provided by performing global implantation gradually lose their effect due to the R-NCE. As a result, V.sub.T is unable to reach an expected value and the MOS transistor can not maintain its normal operation. However, such V.sub.T reduction may cause an increase in the subthreshold current. This leads to a poor reliability for the device while the product yield is reduced.